1. Field of the Invention
The invention relates to an integrated test circuit in an integrated circuit for testing a plurality of internal voltages, a switching device being provided in order to select one of the internal voltages in accordance with a selection signal for the purpose of testing, a comparator device being provided in order to compare a measurement voltage, dependent on the selected internal voltage, with an externally prescribed reference voltage and in order to output an error signal as a result of the comparison.
2. Description of the Related Art
Integrated semiconductor circuits are checked with regard to their correct functioning during and after their production. When testing semiconductor circuits, it is necessary, inter alia, to test voltages generated internally in the semiconductor circuit, i.e. to test whether the internally generated voltage corresponds to the desired voltage. For this purpose, it is usually the case that the internally generated voltages are accessible externally via special test terminals, so that a connected tester device taps off the voltage and can compare the latter with a reference voltage.
In order to save test terminals on the integrated circuit, it is also known, when there are a plurality of internally generated voltages, to provide a multiplexer device which applies the different voltages to a common test terminal provided therefor, under the control of an integrated test circuit or the connected external tester device. Via the common test terminal, the internally generated voltages can then be compared successively with a respective reference voltage and it is thus possible to check whether the internally generated voltage corresponds to the desired voltage.
Generally, the test terminals used for this are available only during the front end test, i.e. in the unsawn state of the integrated semiconductor circuits. The test terminals are no longer accessible after the circuits have been sawn and housed, so that generally it is no longer possible to check the internal voltages. This is disadvantageous since the integrated semiconductor circuit is influenced by test steps which take place after the front end test, by sawing and housing, and the internally generated voltages may change as a result.
A further disadvantage is that, for measuring the voltages, the corresponding resources, i.e. tester channels have to be provided by the tester device. This is disadvantageous in particular when effecting parallel testing of semiconductor circuits, since the semiconductor circuit to be tested has to be connected to the tester device via a relatively large number of tester channels. The relatively large number of test lines reduces the parallelism and thus the throughput when testing semiconductor circuits.